10. CACHE Instructions

10.8 Index Store Tag (I)

Index Store Tag (I) stores the CP0 TagLo and TagHi registers into the primary instruction cache tag array. VA[13:6] defines the address and VA[0] defines the way of the tag to be written.

The following mapping defines the operation:

Tag parity bit = TagLo[0]

State parity bit = TagLo[2]

LRU bit = TagLo[3]

State bit = TagLo[6]

Tag[35:12] = TagLo[31:8]

Tag[39:36] = TagHi[3:0]

All the Tag fields, including parity, are directly written.

Parity check is suppressed for all Index Store Tags.

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

Generated with CERN WebMaker